Tiny Computer specification
Gate Simulator specification
The Net List: To access the Tiny Computer net list, look for this text file on the Novell G drive:
There are some 200+ lines of GateSim specification text in this file, which implements the Tiny Computer (without I/O). You should copy this file onto your own F-drive for editing and testing.
Some of the relevant parts of this file:
20,20,2,40 ; run,ClkRate,PonDly,Trate
The first number (20) is the number of lines to trace in one click of the Run button.
The second number (20) is the number of gate delays in one phase of the system clock. You can experiment with making it run "faster" by reducing this number. Make it too small, and your execution will fail, just like overclocking your PC beyond the circuit capability of the components.
The third number (2) is the power-on resent delay.
The fourth number (40) is the number of gate delays to run for each line of the trace. This is exactly one full phase of the clock, which traces one fetch or one execute cycle at the specified clock rate of 20, making the trace relatively easy to read.
M RAM 16 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 mwr D0 D1 D2 D3...
This line specifies the address (12 bits) and data (16 bits) for the computer memory. The following (two) lines define the actual data to be initially loaded into the simulated memory, as follows:
0 DATA 24583 3 16391 8199The first number on each line is the starting address for these data words. These lines have four words each. This file was assembled from the following source code using the TinyComputer simulator (this program is in the Tester.txt file, also on the G drive):
4 DATA 4 32769 49153 28
; Tiny Computer TestAfter loading the text and assembling it, you can obtain a decimal dump suitable for pasting into the TiCoGate file by clicking on the Data button at the junction of the panel scrollbars in the TinyComputer simulator. If you run your assembled program, the Dump button will capture the memory as modified by your run.
0000 6007 LD X
0001 0003 H NEG
0002 4007 AND X
0003 2007 ADD X
0004 0004 SHR
0005 8001 STO H
0006 C001 JMP H
0007 001C X 28
The Assembly Listing is just the source text with two columns of hexadecimal
numbers prepended to it on the left. The first column is the respective
memory addresses, and the second column is the numeric value of the memory
at that address. The following is a sample assembly listing for a snippet
of TinyComputer code, representing A=(A+3)/2+1, which is loaded into memory
locations 0321 through 0327:
Locn Data Label Mnem Opnds Comments
0321 6326 LD VarA ; get variable
0322 2327 ADD Int3
0323 0004 SHR INC ; both SHR then INC in one cycle
0324 8326 STO VarA
0325 0010 HLT
0326 0000 VarA 0
0327 0003 Int3 3
ALU CHIP 12 Sum.0 Ac.0 Ac.1
This macro implements one bit of the Arithmetic Logic Unit (ALU) in the Tiny Computer, including the accumulator. This macro takes 12 input signals, including eight bits from the Instruction Register, the respective bit from Memory Read, the carry out of the next lower ALU bit, the next higher ALU data bit (for SHR), and a clock to load the Accumulator at the right time. Its outputs are respectively the carry out of the adder, and the true and complement Accumulator bits.
The ALU makes use of the built-in Add macro to do the ADD and INC operations, and three multiplexors to select from the various signals to be added in the ALU and/or loaded into the Accumulator register. The composite operation 0 makes substantial use of a multiplexor to combine the various operations in a single cycle.
PCL Cnt4 PA0.1 PA1.1 PA2.1 PA3.1 Jmp/ Pcnt
PCM Cnt4 PA4.1 PA5.1 PA6.1 PA7.1 Jmp/ PcM
PCH Cnt4 PA8.1 PA9.1 PA10.1 PA11.1 Jmp/ PcH
Three 4-bit counters are combined to form the Program Counter. Note that the count input to the three counters is gated to prevent the upper bits from counting until the lower bits flop over to 0000. There are three jump instructions that cause the PC to be loaded directly from inputs, but one of them requires a +1 to be added to the Instruction Register bits to obtain the correct next instruction address. This complicates the circuitry somewhat.
Ph FF Ph.1 CLK/
The system clock is divided by two to provide Fetch and Execute phases for instruction sequencing. These are further gated to enable register loads (and memory write) to happen at the appropriate times in the cycle. A second flipflop holds the Halt/Run state. It is initialized to 0 (Run) and sets to 1 (Halt) when a HLT instruction executes. The simulator does not stop (it has no way of knowing the significance of this signal), but you can trace the signal to see if the computer halted.
The remainder of the file defines the signals to be traced. There are a number of additional signals commented out. These are sometimes helpful for analyzing why some instruction might be misbehaving. Remarks:
HX HEX Hlt.0 0 0 0 ExecThe left digit on the trace is normally 0, and goes to 1 when the simulated computer halts. The next digit is the instruction Execute phase: 0=Fetch, 1=Execute.
The next three columns are the PC (note it is incremented on the same
clock edge that the instruction register is loaded, so it always seems
to point to the next instruction after the current one executing), the
Instruction Register, and the Accumulator. Following that is the memory
data (as read), and the memory Write signal. The Write signal is
a short pulse in the middle of an instruction execute phase, so when you
are tracing only full cycles, you will not see it. However the trace will
show a memory write event as a separate line.
Rev. 2002 October 18